EC-GSM-IoT Network Synchronization with Support for Large Frequency Offsets

EDGE-based EC-GSM-IoT is a promising candidate for the billion-device cellular IoT (cIoT), providing similar coverage and battery life as NB-IoT. The goal of 20 dB coverage extension compared to EDGE poses significant challenges for the initial network synchronization, which has to be performed well below the thermal noise floor, down to an SNR of -8.5 dB. We present a low-complexity synchronization algorithm supporting up to 50 kHz initial frequency offset, thus enabling the use of a low-cost +/-25 ppm oscillator. The proposed algorithm does not only fulfill the 3GPP requirements, but surpasses them by 3 dB, enabling communication with an SNR of -11.5 dB or a maximum coupling loss of up to 170.5 dB.Comment: Wireless Communications and Networking Conference (WCNC), 201

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm

To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210 uW/MHz

On the optimum design of regulated cascode operational transconductance amplifiers

An optimal design procedure to achieve minimum power consump-tion for a given technology and gain bandwidth is presented. Reg-ulated cascode gain enhancement is used to ensure sufficient DC-gain at minimum gate length transistors. To validate the approach five folded cascode OTA’s have been implemented, spanning a bias range of 1A- 10mA, with measured unity-gain bandwidths within 20 % of the designed value. For 17 mW at 3 V, a 0.5 m CMOS OTA achieves 630 MHz with 51 phase margin. The method has been applied in the design of a 3rd order modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dy-namic range of 86 dB for a 100 kHz input signal bandwidth.

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters

The steeply growing performance demands for highly power- and energy-constrained processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel near-threshold computing (NTC), joining the energy-efficiency benefits of low-voltage operation with the performance typical of parallel systems. Shared-L1-memory multiprocessor clusters are a promising architecture, delivering performance in the order of GOPS and over 100 GOPS/W of energy-efficiency. However, this level of computational efficiency can only be reached by maximizing the effective utilization of the processing elements (PEs) available in the clusters. Along with this effort, the optimization of PE-to-PE synchronization and communication is a critical factor for performance. In this article, we describe a light-weight hardware-accelerated synchronization and communication unit (SCU) for tightly-coupled clusters of processors. We detail the architecture, which enables fine-grain per-PE power management, and its integration into an eight-core cluster of RISC-V processors. To validate the effectiveness of the proposed solution, we implemented the eight-core cluster in advanced 22 nm FDX technology and evaluated performance and energy-efficiency with tunable microbenchmarks and a set of rea-life applications and kernels. The proposed solution allows synchronization-free regions as small as 42 cycles, over 41 smaller than the baseline implementation based on fast test-and-set access to L1 memory when constraining the microbenchmarks to 10 percent synchronization overhead. When evaluated on the real-life DSP-applications, the proposed SCU improves performance by up to 92 and 23 percent on average and energy efficiency by up to 98 and 39 percent on average

Design of plasmonic-waveguiding structures for sensor applications

Surface plasmon resonance has become a widely accepted optical technique for studying biological and chemical interactions. Among others, detecting small changes in analyte concentration in complex solutions remains challenging, e.g., because of the need of distinguishing the interaction of interest from other effects. In our model study, the resolution ability of plasmonic sensing element was enhanced by two ways. Besides an implementation of metal-insulator-metal (MIM) plasmonic nanostructure, we suggest concatenation with waveguiding substructure to achieve mutual coupling of surface plasmon polariton (SPP) with an optical waveguiding mode. The dependence of coupling conditions on the multilayer parameters was analyzed to obtain optimal field intensity enhancement.Web of Science99art. no. 122

Physical Layer Development Framework for OsmocomBB

The open source GSM protocol stack of the OsmocomBB project offers a versatile development environment regarding the data link and network layer. There is no solution available for developing physical layer baseband algorithms in combination with the data link and network layer. In this paper, a baseband development framework architecture with a suitable interface to the protocol stack of OsmocomBB is presented. With the proposed framework, a complete GSM protocol stack can be run and baseband algorithms can be evaluated in a closed system. It closes the gap between physical layer signal processing implementations in Matlab and the upper layers of the OsmocomBB GSM protocol stack. An embedded version of the system has been realized with FPGA and PowerPC to enable real-time operation. The functionality of the system has been verified with a testbed comprising an OpenBTS base-station emulator, a receiver board with RF transceiver and our developed physical layer signal processing syste